1. Field of the Invention
The present invention relates generally to the operation of information processing devices and, more specifically, to a system for asynchronously controlling the access of a plurality of such devices.
2. Description of the Prior Art
The operation of a data processing system calls for the use of a number of input-output devices in cooperation with a central controlling and processing unit, usually called a central processor. Often, if is required that the central processor asks information from, or gives information to, different peripheral devices, such as card readers, card punchers, printers, magnetic tape, or disk recorders, and so on. The operation of such peripheral devices is usually asynchronous. In most cases, operations performed on peripheral devices require time intervals much longer than the ones required by the central processor for controlling the same. In other words, the emission by the central processor of commands and pieces of information, and the reception, by the same, of signals representing the status of the peripheral devices, the checking of such status signals, the reception of data, the performing of operations related to peripherals, require a rather short intervention time, whereas the peripheral units need much longer time intervals for executing the received commands, and for processing the received data. These latter operations are, in any case, controlled in time by a clocking system independent from the clocking system of the central processor.
For an efficient exploitation of the central processor resources, the several peripheral units are therefore, usually operated according to the so-called time-sharing principle, whereby the central processor controls a plurality of peripheral units together, assigning to these units different time intervals. For the same purpose, namely, an efficient exploitation of resources, the assignment of subsequent time intervals to the control of the peripheral units is obtained by an arrangement of interrupt signals controlled by the central processor. Thus, the central processor attends to a peripheral unit only if and when the peripheral unit itself sends one or more suitable signals indicating that it is ready to accept signals from the central processor, or that it is requiring intervention by the central processor.
As no more than one interrupt request may be handled at a time, the central processor provides, by means of suitable selection circuits, attempts to settle the conflicts (which are generated by the simultaneous presence of several interrupt signals) by assigning to the various requests different priority levels and by answering the interrupt requests in the order of decreasing priority. It is known that the various peripheral units, according to the nature and to the particular type of intervention called for, have different timing requirements. For instance, a disk unit, which has to receive or to send data to and from the central processor, may perform these operations only according to a prefixed timing, and the time interval occurring between the transfer of two sequential data is very short. In the case of an asynchronous printer, the reception of a character to be printed may be delayed as long as wanted. Between these extremes there are intermediate requirements.
In U.S. Pat. application Ser. No. 419,312 filed on Nov. 24, 1973, an efficient method for accessing the central processor and assigning the priorities is described. Such an access system organizes the interruption requests according to a double criterion of hierarchy, by carrying out a first partition of the requests according to the priority levels, and then, within each level, further subdividing the requests according to the order of the physical channel employed for the connection to the peripheral units. However, it is subject to the disadvantage that the interrupt requests having the lowest priority are liable to be systematically ignored, because interrupt requests of higher priority may, in practice, monopolize for themselves the interventions of the central processor. This circumstance may typically affect the connection of a bufferized printer to the central processor. A bufferized printer is, of course, a slow peripheral unit, which may accept data within very wide time intervals after the sending of a data request. Such a bufferized peripheral unit may send out a request for a new datum almost immediately after having received a preceding one, even if it may tolerate without inconvenience a remarkable delay in the reception of the requested data. If the priority assigned to the requests of data sent by this device is not the lowest possible, it is clear that this peripheral unit may monopolize the central processor, even if this behavior is not wanted. This would be to the disadvantage of other peripheral units whose interrupt signals have a lower priority. Therefore, the operation of a number of bufferized units at the same time is a remarkably critical operation, since any one of them may become unduly privileged.